Abstract

Hardware accelerators based on Field-Programmable Gate Arrays (FPGAs) and System-on-Chip (SoC) platforms have emerged as indispensable computing engines to meet the extreme throughput and energy efficiency demands of modern artificial intelligence and data-intensive applications. This paper presents a comprehensive review of the design, optimization, and implementation strategies for specialized hardware accelerators. We systematically categorize state-of-the-art acceleration methodologies spanning arithmetic approximation, systolic array architectures, memory hierarchy optimization, and high-level synthesis (HLS) design flows. Furthermore, the review analyzes domain-specific implementations across deep learning inference, vision transformers, and image processing, highlighting key trade-offs between hardware resource utilization, latency, power consumption, and numerical fidelity. Finally, we discuss open research challenges and emerging paradigms, including AI-driven electronic design automation (EDA) and next-generation heterogeneous reconfigurable computing platforms.